|
Hardware design and Functional Languages 2009March 28-29 2009A satellite event of the ETAPS 2009 group of conferences |
Programme
| Saturday, 28 March 2009 | |
| 9:00-9:45 | Satnam Singh: A Bluespec Implementation of an FPGA-based Photoshop Plug-In |
| 9:45-10:30 | Gordon J. Pace and Christian Tabone: Meta-Functional Embedded Languages for Verification of Parametrised Hardware |
| Coffee/Tea | |
| 11:00-11:45 | Magnus O. Myreen, Konrad Slind, Michael J. C. Gordon: Automatic Extraction of Computed Function |
| 11:45-12:30 | Albert Cohen, Louis Mandel, Florence Plateau and Mark Pouzet: Relaxing Synchronous Composition with Clock Abstraction |
| Lunch and time for discussion | |
| 14:00-14:45 | Ingo Sander, Alfonso Acosta and Axel Jantsch: Hardware Design and Synthesis in ForSyDe |
| 14:45-15:30 | Ziyad Hanna and Tom Melham: An Algorithm Level Modelling and Verification Framework for Computer Microarchitectural Design |
| Coffee/Tea | |
| 16:00-16:45 | Koen Claessen, Carl Seger, Mary Sheeran, Emily Shriver and Wouter Swierstra: High level architectural modelling for early estimation of power and performance |
| 16:45-17:30 | Discussion: How can we make architecture description really work? |
| Satilite Events Banquet (additional registration required) | |
| Sundy, 29 March 2009 | |
| 9:00-9:45 | Warren A. Hunt, Jr. and Sol O. Swords: Use of the E Language |
| 9:45-10:30 | Ravi Nanavati: Evolving Numeric Indexing in Bluespec SystemVerilog |
| Coffee/Tea | |
| 11:00-11:45 | Cherif Salama, Walid Taha, Jim Grundy and John O'Leary: The VPP Verilog Preprocessor |
| 11:45-12:30 | Matthew Naylor and Colin Runciman: Improvements to the design and description of the Reduceron |
| Lunch and time for discussion | |
| 14:00-14:45 | Peter Böhm: Towards a Compositional Model of the PCI Express Transaction and Data Link Layers |
| 14:45-15:30 | Dominic Richards and David Lester: Concurrent Functions A System for the Verification of Networks-on-Chip |
| Coffee/Tea | |
| 16:00-16:45 | Gregory Wright: A functional approach to ultra low power chip design using Haskell |
| 16:45-17:30 | Discussion and wrap up |